1. Field of the Invention
The present invention generally relates to measuring critical area in integrated circuit design, and more particularly to a method that uses Voronoi diagrams to measure critical area as the design layout is changed.
2. Description of the Related Art
Within this application several publications are referenced by Arabic numerals within parentheses. Full citations for these, and other, publications may be found at the end of the specification immediately preceding the claims. The disclosures of all these publications in their entireties are hereby expressly incorporated by reference into the present application for the purposes of indicating the background of the present invention and illustrating the state of the art.
Advanced deep sub-micron technology enables millions of transistors to be fabricated on a single die. While this capability grants performance, the smaller size and higher density of layout features adversely affect yield [See: Papadopoulou, E., “Critical area computation for missing material defects in VLSI circuits, ” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 20, No. 5, pp 583-597, May 2001; Fook-Luen Heng and Zhan Chen. “VLSI Yield Enhancement Techniques Through Lay-out Modification.” IBM T. J. Watson Research Center; and A. Venkataraman and I. Koren. “Trade-offs between Yield and Reliability Enhancement.” Proc. of the 1996 IEEE National Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 67-75, November 1996]. Both the manufacturing process and geometry of the layout contribute to this loss of yield.
A part of this yield loss comes from random defects. These defects occur during the manufacturing process and cause electrical faults when the chip is active. The types of electrical faults that may result include, but are not limited to, short-circuits, wire-breaks, and via obstructions. The probability of yield loss due to random defects relates to the critical area of the layout, which can be measured using a Voronoi diagram technique [See: Papadopoulou, E. and Lee, D. T., “Critical area computation via Voronoi diagrams,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 18, No. 4, pp 463-474, April 1999].
Critical area of a very large scale integration (VLSI) layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which represents the main computational problem in the analysis of yield loss due to random (spot) defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: “extra material” defects causing shorts between different conducting regions and “missing material” defects causing open circuits.
In some defect modeling techniques, defects are modeled, consistently, as circles. The underlying reason for modeling defects as circles is the common use of Euclidean geometry. The distance between two points, usually, is measured by the length of the line segment joining the two points. This is the Euclidean distance. The locus of points a unit distance from a center point is usually called the “unit circle”. In Euclidean geometry, the “unit circle” is a circle of radius one.
In reality, spot defects are not necessarily circular. They can have any kind of shape. Therefore, it seems appropriate to use other geometries if the critical area computation can be simplified by modeling defects as squares, diamonds or octagons. For practical purposes, a circular defect can certainly be approximated by a regular octagon. Yield estimation should not considerably depend on which of the above geometries is used to model defects as long as the geometry is chosen consistently. Therefore, the geometry used for a particular computation, preferably, should allow critical area computation in the most efficient way.
A Voronoi diagram can also be used to enhance the computation of critical area. A Voronoi diagram of a set of 2D geometric elements (polygons, line segments, points) is a partition of the plane into regions representing those points in the plane closest to a particular geometric element. Here, “closest” is defined in terms of an appropriate geometry as mentioned above. These regions are called Voronoi cells, each of which is associated with its defining geometric element, called the owner of the cell. The set of points which separates two Voronoi cells is called a Voronoi bisector. The point where three or more Voronoi bisectors (or Voronoi cells) meet is called a Voronoi vertex.
Based on the circuit design and under an appropriate geometry, Voronoi diagrams can be constructed to model the effect of extra-material and missing-material spot defects. The Voronoi diagram partitions the circuit design into Voronoi cells within which defects that occur cause electrical faults between the same two shape edges in the design. This information can then be used to compute critical area. (e.g., see U.S. Pat. Nos. 6,317,859, 6,247,853, and 6,178,539, which are incorporated herein by reference).